Since an all digital phase-locked-loop (ADPLL) may be formed by a CMOS process, a chip size may be made smaller with development in miniaturization and high performance and low-voltage operation may be realized.
In the all digital phase-locked-loop, a time to digital converter (TDC) is used for detecting phase shift between an output signal of an oscillator and a reference signal.
In a conventional time to digital converter, the phase shift between the output signal of the oscillator and the reference signal is calculated using delay time of a delay element as a unit. Therefore, in the conventional time to digital converter, temporal resolution thereof is limited by the delay time of the delay element of one stage and a normalization process to calculate the delay time of the delay element of one stage based on a cycle of the oscillator is necessary.